7. Bibliography

GUIDE: Basics of Electrostatic Discharge (ESD). 7. Bibliography

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7. Bibliography

Key Device and Design Papers EOS/ESD Symposium Proceedings

The following list contains some of the most significant papers on silicon device ESD phenomena and protection design from past proceedings of the EOS/ESD Symposium. After a careful review, the papers were selected based on their original contribution to the field and their effectiveness in advancing the understanding of ESD device phenomena. These papers provide further understanding of the concepts as well as implementation and practical use. This collection of articles will allow new researchers interested in the field to quickly gather pertinent information. The papers are categorized according to the topic of interest. A brief statement on the significance of each paper also is provided.

Copies of the papers may be purchased from the ESD Association

Compiled by: Charvaka Duvvury, May 2000

 

Section A: Device Phenomena

Year

Pages

Authors

Title

Significance

1981

120-131

Pierce & Durgin

An Overview of Electrical Overstress on Semiconductor Devices

Failure physics under ESD and EOS

1983

181-184

Duvvury et al.

A Summary of Effective Electrostatic Discharge Protection Circuits for MOS Memories and Their Observed Failure Modes

Study of npn turn- on of NMOS during ESD and basic ESD design issues

1985

67-76

Pierce

Electro-thermomigration as an Electrical Overstress Mechanism

Study of junction spiking for longer pulses

1988

201-205

Rountree et al.

A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes

SCR design and analysis

1989

167-174

Polgreen & Chatterjee

Improving the ESD Failure Threshold of Silicided nMOS Transistors by Ensuring Uniform Current Flow

Fundamentals of multifinger NMOS behavior under ESD

1989

136-144

Krieger

The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snap-back

Theoretical analysis of MOS bipolar turn-on during ESD

1995

162-174

Duvvury & Amerasekera

Advanced CMOS Device Trigger Mechanisms During CDM

Device behavior and simulations analysis under fast CDM

1999

1-10

Mergens

Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress

Significant work in power device ESD phenomenon

 

Section B: Process & Technology Effects

Year

Pages

Authors

Title

Significance

1987

252-257

Fong & Hu

The Effects of High Electric Field Transients on Thin Gate Oxide MOSFETs

Oxide breakdown behavior under ESD pulses

1988

212-219

Chen

Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors

The first detailed study of NMOS ESD behavior with process changes

1990

143-150

Amerasekera et al.

An Analysis of Low Voltage ESD Damage in Advanced CMOS Processes

Study on the impact drain engineering on ESD damage

1993

117-122

Kuper et al.

Suppression of Soft ESD Failures in a Submicron CMOS Process

Analysis of the effects of LDD on ESD performance

1994

237-245

Amerasekera & Duvvury

The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design

Analysis to establish ESD trends with scaling

1997

308-315

Bock et al.

Influence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 µm CMOS Technology

Study of substrate process on ESD

1997

316-329

Voldman et al.

ESD Robustness and Scaling Implications of Aluminum and Copper Interconnects in Advanced Semiconductor Technology

Current carrying capability of metal interconnects under ESD conditions

1998

161-169

Gupta et al.

ESD-Related Process Effects in Mixed Voltage Sub-0.50 µm Technologies

Study of process parameters on npn characteristics

1999

95-104

Bock

Influence of Gate Length on ESD Performance for Deep Submicron CMOS Technology

A new phenomenon for future technologies

 

Section C: Design Methods

Year

Pages

Authors

Title

Significance

1980

73-80

Keller

Protection of MOS Integrated Circuits from Destruction by Electrostatic Discharge

Fundamentals of ESD protection design

1981

90-96

Hulett

On-Chip Protection of High Density NMOS Devices

Layout effects of ESD protection design

1988

220-227

Maloney

Designing MOS Inputs and Outputs to Avoid Oxide Failure in the Charged Device Model

Failure phenomena & design techniques for CDM protection

1991

88-97

Duvvury & Rountree

A Synthesis of Input Protection Scheme

Analysis and design using discrete ESD device elements

1995

1-12

Maloney & Dabral

Novel Clamp Circuits for IC Power Supply Protection

Protection scheme designs using diode elements in complex circuit approach

1995

43-61

Voldman et al.

Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors

Detailed work on the operation and modeling of diodes

1997

230-239

Chen et al.

Design Methodology for Optimizing Gate-Driven ESD Protection Circuits In Submicron CMOS Processes

Issues related to gate modulated MOS protection

1999

62-69

Smith

An Anti-snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction During EOS/ESD Events

A new design method without using npn snapback in NMOS

 

Section D: Simulations/Modeling

Year

Pages

Authors

Title

Significance

1982

56-61

Pierce

Modeling Metalization Burnout of Integrated Circuits

A model for pulse width dependence of failure current density

1986

41-47

Scott et al.

A Lumped Element Model for Simulation of ESD Failures in Silicon Devices

Theoretical model that studied the effect of contact resistance for ESD

1988

137-146

Pierce

Electrical Overstress Testing of a 256K UVEPROM to Rectangular and Double Exponential Pulse

Modeling work that allows conversion to different types of waveforms

1993

73-80

Lin

ESD Sensitivity and VLSI Technology Trends: Thermal Breakdown and Dielectric Breakdown

Theoretical model to predict thermal and oxide breakdown sensitivities

1996

265-275

Beebe

Methodology for Layout Design and Optimization of ESD Protection Transistors

Analytical study of NMOS layout for ESD performance

 

Section E: Measurement/Characterization

Year

Pages

Authors

Title

Significance

1985

49-54

Maloney & Khurana

Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena

A pulsed method to measure ESD data

1989

59-71

Renninger et al.

A Field-Induced Charged Device Model Simulator

Description and operation of the CDM simulator

1990

119-130

Roozendaal et al.

Standard ESD Testing of Integrated Circuits

A comprehensive study of testers and parasitics

1992

129-134

Maloney

Integrated Circuit Metal in the Charged Device Model: Bootstrap Heating, Melt Damage and Scaling Laws

Metal heating under CDM events

1993

129-137

Verhaege et al.

Analysis of HBM ESD Testers and Specifications Using 4th Order Lumped Element Model

Analysis of HBM with parasitics

1998

170-176

Notermans et al.

Pitfalls When Correlating TLP, HBM, and MM Testing

Gives proper method to interpret data from pulse testing

1999

28-37

Wolf

Analyzing the Switching Behavior of ESD Protection Transistors by Very Fast Transmission Line Pulsing

A new test method to understand ESD behavior

1999

212-224

Voldman

A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies

The first paper to present ESD layout methods

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