Key Device and Design Papers EOS/ESD Symposium Proceedings
The following list contains some of the most significant papers on silicon device ESD phenomena and protection design from past proceedings of the EOS/ESD Symposium. After a careful review, the papers were selected based on their original contribution to the field and their effectiveness in advancing the understanding of ESD device phenomena. These papers provide further understanding of the concepts as well as implementation and practical use. This collection of articles will allow new researchers interested in the field to quickly gather pertinent information. The papers are categorized according to the topic of interest. A brief statement on the significance of each paper also is provided.
Copies of the papers may be purchased from the ESD Association
Compiled by: Charvaka Duvvury, May 2000
Section A: Device Phenomena
Pierce & Durgin
An Overview of Electrical Overstress on Semiconductor Devices
Failure physics under ESD and EOS
Duvvury et al.
A Summary of Effective Electrostatic Discharge Protection Circuits for MOS Memories and Their Observed Failure Modes
Study of npn turn- on of NMOS during ESD and basic ESD design issues
Electro-thermomigration as an Electrical Overstress Mechanism
Study of junction spiking for longer pulses
Rountree et al.
A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes
SCR design and analysis
Polgreen & Chatterjee
Improving the ESD Failure Threshold of Silicided nMOS Transistors by Ensuring Uniform Current Flow
Fundamentals of multifinger NMOS behavior under ESD
The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snap-back
Theoretical analysis of MOS bipolar turn-on during ESD
Duvvury & Amerasekera
Advanced CMOS Device Trigger Mechanisms During CDM
Device behavior and simulations analysis under fast CDM
Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress
Significant work in power device ESD phenomenon
Section B: Process & Technology Effects
Fong & Hu
The Effects of High Electric Field Transients on Thin Gate Oxide MOSFETs
Oxide breakdown behavior under ESD pulses
Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors
The first detailed study of NMOS ESD behavior with process changes
Amerasekera et al.
An Analysis of Low Voltage ESD Damage in Advanced CMOS Processes
Study on the impact drain engineering on ESD damage
Kuper et al.
Suppression of Soft ESD Failures in a Submicron CMOS Process
Analysis of the effects of LDD on ESD performance
Amerasekera & Duvvury
The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design
Analysis to establish ESD trends with scaling
Bock et al.
Influence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 µm CMOS Technology
Study of substrate process on ESD
Voldman et al.
ESD Robustness and Scaling Implications of Aluminum and Copper Interconnects in Advanced Semiconductor Technology
Current carrying capability of metal interconnects under ESD conditions
Gupta et al.
ESD-Related Process Effects in Mixed Voltage Sub-0.50 µm Technologies
Study of process parameters on npn characteristics
Influence of Gate Length on ESD Performance for Deep Submicron CMOS Technology
A new phenomenon for future technologies
Section C: Design Methods
Protection of MOS Integrated Circuits from Destruction by Electrostatic Discharge
Fundamentals of ESD protection design
On-Chip Protection of High Density NMOS Devices
Layout effects of ESD protection design
Designing MOS Inputs and Outputs to Avoid Oxide Failure in the Charged Device Model
Failure phenomena & design techniques for CDM protection
Duvvury & Rountree
A Synthesis of Input Protection Scheme
Analysis and design using discrete ESD device elements
Maloney & Dabral
Novel Clamp Circuits for IC Power Supply Protection
Protection scheme designs using diode elements in complex circuit approach
Voldman et al.
Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors
Detailed work on the operation and modeling of diodes
Chen et al.
Design Methodology for Optimizing Gate-Driven ESD Protection Circuits In Submicron CMOS Processes
Issues related to gate modulated MOS protection
An Anti-snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction During EOS/ESD Events
A new design method without using npn snapback in NMOS
Section D: Simulations/Modeling
Modeling Metalization Burnout of Integrated Circuits
A model for pulse width dependence of failure current density
Scott et al.
A Lumped Element Model for Simulation of ESD Failures in Silicon Devices
Theoretical model that studied the effect of contact resistance for ESD
Electrical Overstress Testing of a 256K UVEPROM to Rectangular and Double Exponential Pulse
Modeling work that allows conversion to different types of waveforms
ESD Sensitivity and VLSI Technology Trends: Thermal Breakdown and Dielectric Breakdown
Theoretical model to predict thermal and oxide breakdown sensitivities
Methodology for Layout Design and Optimization of ESD Protection Transistors
Analytical study of NMOS layout for ESD performance
Section E: Measurement/Characterization
Maloney & Khurana
Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena
A pulsed method to measure ESD data
Renninger et al.
A Field-Induced Charged Device Model Simulator
Description and operation of the CDM simulator
Roozendaal et al.
Standard ESD Testing of Integrated Circuits
A comprehensive study of testers and parasitics
Integrated Circuit Metal in the Charged Device Model: Bootstrap Heating, Melt Damage and Scaling Laws
Metal heating under CDM events
Verhaege et al.
Analysis of HBM ESD Testers and Specifications Using 4th Order Lumped Element Model
Analysis of HBM with parasitics
Notermans et al.
Pitfalls When Correlating TLP, HBM, and MM Testing
Gives proper method to interpret data from pulse testing
Analyzing the Switching Behavior of ESD Protection Transistors by Very Fast Transmission Line Pulsing
A new test method to understand ESD behavior
A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies
The first paper to present ESD layout methods